Chip manufacturers continually strive to improve the quality and reliability of their products. In recent years, so-called “design for test” (DFT) practices that incorporate testing mechanisms into the design of a semiconductor chip have become prevalent in the semiconductor industry. In particular, many semiconductor chips are now designed to incorporate so-called “scan chains” wherein logic components (e.g. transistors, logic circuits) are interconnected such that a testing vector applied at the beginning of the chain propagates through each of the interconnected devices. The output signal received from the end of the scan chain can then be compared against an expected value to determine if any faults exist in the scan chain. In the widely-adopted “stuck at” test, for example, a testing vector is applied to a scan chain for identifying devices within the chain that are acting as if they are “stuck at” a logic low (“0”) or high (“1”) value. Vectors are also applied to the scan chains during “IDDQ” testing, which typically measures changes to the quiescent supply current provided to the device under test. Other testing techniques that can apply logic vectors to scan chains include “AC” tests that isolate chip faults relating to timing issues based upon dynamic transition errors, and the like.
Using traditional automatic test pattern generation (ATPG) techniques, an external testing device typically applies input vectors to the scan chains and reads the resulting outputs via interface pins on the semiconductor chip. This technique allows for relatively high flexibility in applying deterministic signals, controlling the speed of the test and processing the received data. IDDQ tests, in particular, have been historically best suited to external application due to the relative delays in measuring supply current. Externally testing devices can be complicated and expensive, however, and can require that additional test interface pins be built into certain chips for adequate testing. Moreover, the time for an external tester to conduct a thorough test of a chip can be undesirably long, leading many engineers to seek faster testing alternatives.
As a result, many chips now incorporate built-in self test (BIST) modules that internally generate pseudo-random vectors, apply the vectors to the scan chains, and receive a result that can be evaluated. Internal BIST testing is generally very fast compared to externally-applied testing, but can be somewhat limited in flexibility. In particular, the vectors available at any particular time can be somewhat limited to those produced by the pseudo-random pattern generator (PRPG) in the logic BIST. Because the ability to control the vectors and the timing of the logic BIST testing is somewhat reduced in comparison to externally-applied testing, logic BIST testing is typically limited to stuck-at and AC-type tests.
As semiconductor chips and their associated manufacturing techniques become increasingly complex, however, it is becoming increasingly common to supplement conventional “stuck-at” testing with other tests (such as IDDQ) to increase the level of fault detection and therefore enhance the reliability of the device under test. These additional tests, however, are typically performed using complicated, expensive and time consuming external testing devices. Moreover, performing multiple tests on a chip typically involves separately generating and applying multiple distinct vector sets to the scan chains, thereby further complicating the test process and increasing the test time. As a result, it is desirable to formulate a technique for efficiently testing the logic contained within a semiconductor chip without adversely affecting test coverage. In addition, it is desirable to create a tool and a test device for implementing efficient and effective testing techiques. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.